Processor "in slow motion" and its system-on-chip

Want to see how industrial processor "in slow motion"? As instructions pass from stage to stage of the pipeline, as the read requests from the memory of the fall or miss the cache? How about to build their system-on-chip, using the same microprocessor core, which is used by Samsung engineers in the new platform Artik 1? If Yes, then this announcement is for you:



Dear teacher of computer architecture, circuit design or system programming

Developer of microprocessor cores MIPS, Imagination Technologies company, in cooperation with the leading Russian universities and manufacturer of microcontrollers Microchip Technology announces a series of seminars in Russia, dedicated to the new product for education — MIPSfpga. Four free one-day seminar dedicated to MIPSfpga, will be held from 26 to 30 October at the universities of Moscow, Zelenograd and St. Petersburg. In addition, MIPSfpga will be provided on a separate, paid the Microchip Masters seminar Russia in St. Petersburg / Sochi.

Website to register for the seminars MIPSfpga in universities
bit.ly/mipsfpga-russia-registration

Website to register the Microchip Masters seminar Russia
bit.ly/microchip-masters-russia-registration

MIPSfpga — licensed for free to universities source industrial microprocessor core MIPS microAptiv UP. This kernel is used as the basis of the Microchip PIC32MZ microcontroller, as well as a new platform for the Internet of things — Samsung Artik 1.

The kernel MIPS microAptiv UP used in industry, together with standard over the past 25 years the technological process of IC design, in which the processor and other system components on the chip are designed in the hardware description language Verilog, and then a description through several transformations turns into a mask, which are manufactured in the factory chip.

The educational version of the MIPS microAptiv UP — MIPSfpga — uses an alternative way of implementation: description of the system is transformed into the configuration files for cheap student boards with field programmable gate arrays (FPGAS), which are often called programmable logic integrated circuits (FPGA) or Field Programmable Gate Array (FPGA).

This decision opens many possibilities for education:

the
1. Students can build their own prototypes of systems-on-chip, coupling the microprocessor core, memory and designed their device I / o
the
2. Internal registers can be connected to the output ports and output information about the current state of the processor pipeline, caches, and device memory management. After that, the engine can be run at a low clock frequency and to observe his work "in slow motion".
the
3. Students can experiment with their options of caches to design a multi-core system with specialized coprocessors, eksperimentirovat with the division of tasks into hardware and software part.

Thus MIPSfpga occupies a niche between simplistic academic implementations of the MIPS, which are traditionally used in courses at the microarchitecture — and finished industrial processors, in which students learn the embedded systems programming. MIPSfpga is an ideal platform for teaching systems thinking at the interface between equipment design and programming.

Places and dates of the seminars on MIPSfpga, companies and responsible instructors

The instructor from Imagination Technologies — Yuri Panchul, senior engineer development equipment, office MIPS processors

October 26, 2015 — Moscow / Zelenograd, national research University "Moscow Institute of electronic technology" (MIET). Instructors:
the

the
• Alexey Pereverzev, Ph. D., associate Professor, head of Department of computer science
the
• Peter Andreev, lead programmer
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• Evgeniy Liventsev and Alexander Silantyev, assistants

27 October — Moscow, Moscow state University named after M. V. Lomonosov (MSU). Instructors:

the

the
• Shupletsov Mikhail, candidate of pH.-PhD, assistant Professor, Department of mathematical Cybernetics, faculty of computational mathematics and Cybernetics
the
• Vladislav Podymov, K. f.-M. SC., Junior researcher, Department of mathematical Cybernetics, faculty of computational mathematics and Cybernetics
the
• Boris Danilov, Junior researcher, Department of mathematical Cybernetics, faculty of computational mathematics and Cybernetics

the seminar is supervised by the head of the master program "Discrete control systems and their applications", D. SC.M. D., Deputy Dean for science and Finance, Professor, Department of mathematical Cybernetics, faculty of computational mathematics and Cybernetics, Sergei A. Lozhkin.

October 28 — Moscow, national research nuclear University "MIFI", formerly Moscow engineering-physical Institute. Instructor:

the

the
• Maksim Gorbunov, Ph. D., associate Professor of Department of Micro - and nanoelectronics, national research nuclear University MEPhI, Deputy head. Department of FGU FNTS srisa RAS

October 29 — St. Petersburg / Irkutsk, the hotel "aquamarine", Microchip Masters conference in Russia, organized by Gamma Saint Petersburg, the official distributor of Microchip Technology in Russia.

the

the
• On Microchip Masters Russia is only an hour and a half presentation about MIPSfpga, not a full workshop, as in the universities.

October 30 — St. Petersburg, University ITMO, formerly St. Petersburg national research University of information technologies, mechanics and optics. Instructors:

the

the
• Alexey Platunov, Ph. D., Professor, DEP. computing machinery
the
• Pavel Kustarev V. Ph. D., Assoc. DEP. computing machinery
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• Graduate students, DEP. computing Bykovskiy Sergey, Antonov Alexander, Analou novel, Pinkevich Basil

table of Contents seminars in universities

the
1. Welcome to the seminar.
the
2. a Short story about educational programs Imagination Technologies, a review of the company-developed processor cores and their applications.
the
3. a Brief overview of the architecture (instruction) MIPS microarchitecture (conveyor device) kernel MIPSfpga and some of its units, caches and device management virtual memory.
the
4. Demonstration of modeling the minimal system with processor core MIPSfpga using the simulator Mentor ModelSim Student Edition. Project creation, simulation, load in the simulated system of the user program analysis results in the timing diagram.
the
5. Demonstration of synthesis, placement and trace system kernel MIPSfpga in Xilinx Vivado environment. The new project, setting time restrictions on the use of IP blocks from Xilinx. Overview of the synthesized circuits at different stages, interpretation of the report on the timing and utilization of the FPGA resources.
the
6. Demonstration download of the synthesized system in the configuration memory of the FPGA on the Digilent Nexys4 DDR Board with a Xilinx FPGA Artix-7.
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7. demonstrates the use of package Codescape for cross-compiling embedded programs written in C and assembler and convert them to formats suitable for work in the simulated system, and for downloading in to FPGA.
the
8. Demonstration of the connection cross-debugger, running on a personal computer with the system on the FPGA using the debug adapter BusBlaster, package OpenOCD and the interface EJTAG core MIPSfpga.
the
9. Discussion of porting MIPSfpga on boards with other FPGA.
the
10. Laboratory work in which the participants implement in the Verilog language simple peripheral devices that simulate the system on the ModelSim simulator, synthesized using Xilinx Vivado, upload the result to the Board with the FPGA, use the Codescape package for cross-compiling programs and cross-debugging to work with the system through a debug adapter.
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11. Conclusion, questions and answers.

Check

Participation in seminars at universities for employees of educational institutions free of charge, but places are limited, so please register in advance.

Universities-the organizers will provide for seminars computer classes, but Imagination Technologies provides FPGA Board but if you can, we recommend you to bring your own laptop with 64-bit Windows 7 or Windows 8, on which is installed the latest version of Xilinx Vivado with a working license (free or paid) for RTL synthesis Artix-7 FPGA. It is also advisable to pre-register in the educational program Imagination and download packages MIPSfpga Getting Started and MIPSfpga Fundamentals. The package installer Essentials and Codescape software OpenOCD to work with the debug adapter BusBlaster is inside the package MIPSfpga Getting Started.

If you want the seminar to refresh knowledge on the fundamentals of digital logic, concepts of hardware description languages, concepts of assembler, architecture and microarchitecture of processors, we recommend you to download a free Russian translation of the popular textbook David Harris and Sarah Harris “Digital design and computer architecture”, a PDF file which is also available on the website of the educational programs Imagination Technologies.

Waiting for you at the workshop!

Robert Owen,



Manager of University programs
Imagination Technologies
e-mail: Robert.Owen@imgtec.com
Web: community.imgtec.com/university

Article based on information from habrahabr.ru